Nonvolatile semiconductor memory device and method for manufacturing the same
US9006812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Aug 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In general, according to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral region. The memory cell region includes first element isolation regions, first semiconductor regions, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. The first element isolation regions separate a semiconductor layer and include a first insulating film. The first semiconductor regions are separated by the first element isolation regions. The peripheral region includes a second element isolation region a second insulating film. Each of the first element isolation regions includes a first and a second portion. A step is present between the first and the second portion. At least part of a side surface and a lower end of the second element isolation region are surrounded by the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.