Method and apparatus for power amplifier linearization
US9007128B2 · kind B2 · utility
1Cited by
25References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2011 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Dec 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45684
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a circuit includes a variable group delay configured to delay a wideband input signal to obtain a delayed input signal; a wideband operational amplifier configured to determine an error signal based on a difference between the delayed input signal and a linearized power amplifier output; a feedback amplifier configured to amplify the error signal to obtain an amplified error signal; and a directional combiner configured to combine the amplified error signal with the power amplifier output to obtain the linearized power amplifier output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.