Memory channel selection in a multi-channel memory
US9009441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2012 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Jan 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, this disclosure describes techniques for selecting a memory channel in a multi-channel memory system for storing data, so that usage of the memory channels is well-balanced. A request to write data to a logical memory address of a memory system may be received. The logical memory address may include a logical page number and a page offset, where the logical page number maps to a physical page number and the logical memory address maps to a physical memory address. A memory unit out of a plurality of memory units in the memory system may be determined by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number. The data may be written to a physical memory address in the determined memory unit in the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.