Patent · US Active

Memory subsystem command bus stress testing

US9009540B2 · kind B2 · utility

8Cited by

36References

30Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Christopher P. Mozak · Beaverton, US
Theodore Z. Schoenborn · Portland, US
James M. Shehadi · Portland, US
David G. Ellis · Tualatin, US
Tomer Levy · Nes Ziona, IL
Zvika Greenfield · Kfar Sava, IL

Key dates

Filing date	Dec 5, 2012
Grant date	Apr 14, 2015
Priority date	—
Expiry date	Jun 18, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/52
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.