Methods for patterning microelectronic devices using two sacrificial layers
US9012326B2 · kind B2 · utility
35Cited by
1References
45Claims
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Key dates
| Filing date | Apr 14, 2011 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Sep 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.