Memory device with die stacking and heat dissipation
US9013040B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2013 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Oct 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16152
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device with die stacking is provided. A plurality of substrates layers are stacked together into a stack. Each substrate layer may include a substrate having a plurality of cavities to receive integrated circuit components within the thickness of the substrate. A plurality of conductive spheres are arranged between at least two adjacent substrate layers and are electrically coupled to the integrated circuit components in at least one of the two adjacent substrates. The two adjacent substrate layers of the stack include: (a) a first substrate having a first plurality of cavities to receive integrated circuit components, and (b) a second substrate having a second plurality of cavities to receive integrated circuit components, wherein the first plurality of cavities is offset from a second plurality of cavities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.