Low power display port with arbitrary link clock frequency
US9013493B2 · kind B2 · utility
0Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2012 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | May 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/006
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.