Memory with redundant sense amplifier
US9013933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2014 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Jun 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.