Memory architecture for display device and control method thereof
US9013948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2014 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Feb 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.