Methods and systems for power-efficient inductive chip-to-chip communications
US9014295B1 · kind B1 · utility
5Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2013 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Aug 12, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Digital information is communicated between stacked integrated circuit devices by inductive coupling between arrays of inductors formed from integrated circuit wiring layers. This can be done using a combination of push-pull drivers, common inductor return legs, and balanced sparse ternary encoding. Embodiments result in low power utilization and high pin efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.