Patent · US Active

Clock synchronizer for aligning remote devices

US9014323B2 · kind B2 · utility

3Cited by

8References

20Claims

0Family size

Assignee

NXP B.V. · NL

Inventors

Jos Verlinden · Wachtendonk, DE
Remco Cornelis Herman van de Beek · Eindhoven, NL

Key dates

Filing date	Aug 30, 2013
Grant date	Apr 21, 2015
Priority date	—
Expiry date	Aug 30, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/0079
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.