System and method incorporating an arithmetic logic unit for emulation
US9015026B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 2010 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Jun 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for verifying logic circuit designs having arithmetic operations and complex logical operations such that the operations may be evaluated at substantially full hardware speed is disclosed. According to one embodiment, a system for verifying the functionalities of an electronic circuit design comprises hardware emulation resources emulating at least a portion of an electronic circuit design; and a first hardware ALU block having an arithmetic logic unit that performs an arithmetic operation or a complex logical operation of the electronic circuit design, and a set of flag registers that contains a conditional value for enabling the arithmetic logic unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.