Mechanism for low power standby mode control circuit
US9015509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2012 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | May 7, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.