Decoding apparatus with de-interleaving efforts distributed to different decoding phases and related decoding method thereof
US9015551B2 · kind B2 · utility
1Cited by
5References
22Claims
0Family size
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Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Sep 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2714
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoding apparatus includes a memory device and a decoding circuit. The memory device is arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows. The decoding circuit is coupled to the memory device. The decoding circuit is arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.