Simultaneous data transfer and error control to reduce latency and improve throughput to a host
US9015557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/004
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.