Method for forming interposers and stacked memory devices
US9016552B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 2014 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Mar 17, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming a stacking interposer are provided that create a more compact and/or reliable interposer cavity. According to one method, a segmentation process that partially cuts a multi-cell, multi-layer PCB panel to a controlled depth along the internal walls/edges of a cavity region with each of the interposer cell sites defined within the PCB panel is used. The material within the cavity region is then removed (by routing) to a controlled depth to form the internal cavity for each interposer cell site. Pillars may then be removed from the PCB panel. As a result of the initial partial cuts of the internal walls of the cavity region, the corners of the cavities may have a square configuration for fitting over the top of a BGA/memory device (which has very square corners).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.