Semiconductor device
US9018756B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Nov 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stress relief layers are each provided on each circuit on an insulating substrate in a semiconductor module; a metal base coming into contact with the semiconductor module is divided into a thinned and low stiffened first metal base and a thickened and high stiffened second metal base; and the semiconductor module is bonded to the first metal base and then the first and the second metal bases are bonded to be integrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.