Delay time adjusting circuit, method, and integrated circuit
US9018998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Dec 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/131
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.