Gate driver for enhancement-mode and depletion-mode wide bandgap semiconductor JFETs
US9019001B2 · kind B2 · utility
8Cited by
29References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2012 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | May 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/6875
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.