Patent · US Active

Memory and method of operating the same

US9019740B2 · kind B2 · utility

0Cited by

9References

17Claims

0Family size

Assignee

Shanghai Huahong Grace Semiconductor Manufacturing Corporation · CN

Inventors

Hong Jiang · Shanghai, CN
Yi Xu · Menlo Park, US
Jun Xiao · Fremont, US
Weiran Kong · Shanghai, CN
Binghan Li · Shanghai, CN

Key dates

Filing date	Nov 19, 2012
Grant date	Apr 28, 2015
Priority date	—
Expiry date	Jun 14, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/037
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory includes an array of memory cells including a plurality of memory cells with a common source, wherein each of the plurality of memory cells with a common source includes two sub-memory cells, each of the sub-memory cells corresponds to a bit line, and the respective bits are electrically independent. Each of the sub-memory cells in the memory according to the disclosure corresponds to a bit line, and the respective bit lines are electrically independent, thereby effectively avoiding interference to other memory cells which will not be programmed during a program operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.