Dual rail memory architecture
US9019782B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 2012 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Mar 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in groups of a first direction and groups of a second direction. Each amplifying circuit is coupled to a plurality of first memory cells arranged in a first group of the first direction via a first data line. The first driver circuit is configured to drive the plurality of first amplifying circuits. The first level shifter is configured to level shift an input signal operating in a first power domain to an output signal operating in a second power domain. The output signal of the first level shifter is for use by the first driver circuit. The first driver circuit and a sense amplifier of an amplifying circuit operate in the second power domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.