Debug access mechanism for duplicate tag storage
US9021306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2012 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Aug 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.