Flash memory read error recovery with soft-decision decode

US9021332B2 · kind B2 · utility

Assignee

• Seagate Technology LLC · US

Inventors

• Erich F. Haratsch · San Jose, US
• Jeremy Werner · San Jose, US
• Zhengang Chen · San Jose, US
• Earl T. Cohen · Milpitas, US
• Yunxiang Wu · Cupertino, US
• Ning Chen · Harvard, US

Key dates

• Filing date: Mar 13, 2013
• Grant date: Apr 28, 2015
• Expiry date: May 19, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M13/41
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.