Method and design of an RF thru-via interconnect
US9024326B2 · kind B2 · utility
1Cited by
4References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 18, 2012 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Nov 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.