Photolithography alignment mark, mask and semiconductor wafer containing the same mark
US9024456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2011 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Dec 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.