Input buffer circuit
US9024653B2 · kind B2 · utility
0Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Apr 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.