Patent · US Active

System and method for controlling circuit input-output timing

US9024670B2 · kind B2 · utility

1Cited by
4References
16Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 8, 2013
Grant dateMay 5, 2015
Priority date
Expiry dateOct 8, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K5/131
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.