Negative level shifter
US9024674B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter including a differential input stage including first and second transistors having respective first terminals, respective control terminals configured to receive a differential input signal, and respective second terminals connected in common to a first voltage; a breakdown voltage controller including third and fourth transistors having respective first terminals, respective second terminals connected to respective first terminals of the first and second transistors, and respective control terminals configured to receive a bias signal, and a load stage comprising fifth and sixth transistors having respective first terminals connected to respective first terminals of the third and fourth transistors, respective control terminals that are cross coupled, and respective second terminals connected to a second voltage is disclosed. A bias voltage applied to bulks or bodies of the first through the fourth transistors equals or substantially equals the first voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.