Signal processing circuit, inverter circuit, buffer circuit, driver circuit, level shifter, and display device
US9024681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2011 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Oct 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0291
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.