Patent · US Active

Reconfigurable equalization architecture for high-speed receivers

US9025654B1 · kind B1 · utility

3Cited by

5References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Xiaoyan Su · San Jose, US
Sriram Narayan · Pleasanton, US
Sergey Shumarayev · Los Altos Hills, US

Key dates

Filing date	Sep 16, 2013
Grant date	May 5, 2015
Priority date	—
Expiry date	Oct 24, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH04L25/03038
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.