Floating-tap decision feedback equalizer
US9025656B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Dec 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03585
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a floating-tap decision feedback equalization (DFE) circuit. In an exemplary implementation, the floating-tap DFE circuit may include a high-speed shift register, a deserializer and data selector, a bypass deserializer, a high-speed multiplexer and a tap generation circuit. In one aspect of the invention, the floating-tap DFE circuit may advantageously cover an entire tap range beyond a fixed tap range without holes over a range of data rates. Other embodiments, aspects and features are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.