Method and apparatus for implementing slice-level adjustment
US9025702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Apr 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.