Patent · US Active

Interface system, and corresponding integrated circuit and method

US9026761B2 · kind B2 · utility

10Cited by
7References
15Claims
0Family size

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Key dates

Filing dateDec 13, 2011
Grant dateMay 5, 2015
Priority date
Expiry dateApr 23, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F1/12
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

An interface system for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal, a first data signal when a first control signal indicates that the first data signal contains valid data, and wherein the asynchronous circuit generates a second data signal according to an asynchronous communication protocol. The system includes a FIFO memory, a control circuit for asynchronously writing the second data signal in the memory when the second data signal indicates the start of a communication, and synchronously reading the second data signal from the memory in response to a clock signal, and a conversion circuit for decoding, according to a asynchronous communication protocol, the second data signal read from the memory in a decoded data signal, wherein the decoded data signal corresponds to the first data signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.