Memory system performing wear leveling based on deletion request
US9026764B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2012 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Jul 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system of a embodiments includes a first storing area having physical blocks and a second storing area recording a logical to physical translation table and an erasure count table keeping data erasure count in physical blocks. The memory system of the embodiments includes a controller which, when a logical address for deletion is notified, obtains data erasure count of a deletion physical block including a deletion area specified by the physical address corresponding to the logical address, and when a physical block having a small erasure count not more than a predetermined rate of the data erasure count exists in the erasure count table, reads out valid data for the memory system in the physical block having a small erasure count onto the second storing area, writes the above data into the deletion area, and invalidates the valid data in the physical block having a small erasure count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.