Systematic mitigation of memory errors
US9026889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2014 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Jan 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.