Patent · US Active

Method and system for double patterning technology (DPT) odd loop visualization for an integrated circuit layout

US9026958B1 · kind B1 · utility

6Cited by

5References

26Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Sanjib Ghosh · Sidhauli, IN
Harindranath Parameswaran · Noida, IN
Henry Yu · Palo Alto, US

Key dates

Filing date	Mar 11, 2013
Grant date	May 5, 2015
Priority date	—
Expiry date	Mar 11, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG03F7/70466
WIPO fieldOptics
WIPO sectorInstruments

Abstract

Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.