Patent · US Active

System and method for fault sensitivity analysis of mixed-signal integrated circuit designs

US9026963B1 · kind B1 · utility

3Cited by

14References

19Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Donald J. O'Riordan · Sunnyvale, US
Ilya Yusim · San Jose, US
Zhipeng Liu · Fairfax, US

Key dates

Filing date	Feb 24, 2014
Grant date	May 5, 2015
Priority date	—
Expiry date	Mar 1, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3167
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.