Semiconductor integrated circuit, method of designing the same, and method of fabricating the same
US9026975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.