Self-aligning hybridization method
US9029259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2012 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Mar 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.