Active matrix display panel with ground tie lines
US9029880B2 · kind B2 · utility
28Cited by
45References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Apr 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. A ground line is located in the non-pixel area and an array of ground tie lines run between the bank openings in the pixel area and are electrically connected to the ground line in the non-pixel area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.