Linearization circuit and related techniques
US9030255B2 · kind B2 · utility
3Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2013 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Jun 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2201/3221
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and techniques to linearize the operation of an RF power amplifier are described. A linearizer circuit may include a non-amplification signal path which includes a delay line and an amplification signal path which includes at least one amplifier stage. In some embodiments, the amplification signal path may include an odd number of amplification stages. The linearizer may be used to precondition an input signal of an RF power amplifier in a manner that improves the overall linearity of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.