Hybrid display frame buffer for display subsystem
US9030482B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2012 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Apr 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A hybrid display frame buffer for a display subsystem. An embodiment of an apparatus a first logic to split a video image into a first data portion and a second data portion; a display frame buffer including a first memory component having a first type of memory and a second memory component having a second type of memory, the first logic to write the first data portion to the first memory component and the second data portion to the second memory component; and a second logic to read the first data portion from the first memory component and the second data component from the second memory component, and to combine the first data portion and the second data portion to generate a combined video image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.