Low profile, space efficient circuit shields
US9030841B2 · kind B2 · utility
6Cited by
21References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2012 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Aug 23, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low profile, space efficient circuit shield is disclosed. The shield includes top and bottom metal layers disposed on the top of and below an integrated circuit. In one embodiment the shield can include edge plating arranged to encircle the edges of the integrated circuit and couple the top and bottom metal layers together. In another embodiment, the shield can include through vias arranged to encircle the edges of the integrated circuit and couple the top and bottom metal layers together. In yet another embodiment, passive components can be disposed adjacent to the integrated circuit within the shield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.