Switch having dedicated stacking link
US9031065B2 · kind B2 · utility
0Cited by
10References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2012 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Oct 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A first switch includes a processor and a memory communicatively coupled to the processor. The memory stores instructions causing the processor, after execution of the instructions by the processor, to establish a first stacking link between a first stacking port of the first switch and a first stacking port of a second switch, establish a second stacking link between a second stacking port of the first switch and a first stacking port of a third switch, and dedicate the first stacking link to a first class of traffic between the first switch and the second switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.