Data prefetcher with complex stride predictor
US9032159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2012 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Jan 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware data prefetcher includes a queue of indexed storage elements into which are queued strides associated with a stream of temporally adjacent load requests. Each stride is a difference between cache line offsets of memory addresses of respective adjacent load requests. Hardware logic calculates a current stride between a current load request and a newest previous load request. The hardware logic compares the current stride and a stride M in the queue and compares the newest of the queued strides with a queued stride M+1, which is older than and adjacent to stride M. When the comparisons match, the hardware logic prefetches a cache line whose offset is the sum of the offset of the current load request and a stride M−1. Stride M−1 is newer than and adjacent to stride M in the queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.