Recovering from an error in a fault tolerant computer system
US9032190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2010 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Oct 19, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1629
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.