Test method for nonvolatile memory
US9032264B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Nov 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a test method for testing a nonvolatile semiconductor memory including first and second areas includes performing first to sixth processes every block included in the first area. The first process performs block erase. The second process writes data to a first block. The third process reads data from first pages except a second page in the first block. The fourth process reads data from the second page. The fifth process records an event of a first read error in the second area when a read error happens in the third process. The sixth process records an event of a second read error in the second area when a read error happens in the fourth process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.