Parallel low and asymmetric rate Reed Solomon coding
US9032277B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2012 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Jun 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.