Integrated circuit floorplan for compact clock distribution
US9032358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2013 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Mar 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2113/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.