JFET ESD protection circuit for low voltage applications
US9035363B2 · kind B2 · utility
1Cited by
13References
19Claims
0Family size
Inventor
Key dates
| Filing date | Aug 1, 2014 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Aug 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/87
Abstract
An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first region having a first conductivity type (410) is formed at a face of a substrate. A gate having a second conductivity type (406) is formed in the substrate beside the first region. A channel having the first conductivity type is formed below the first region adjacent the gate. A second region having the first conductivity type (404) is formed at the face of the substrate beside the gate. A third region having the first conductivity type (430) is formed below the channel and has a greater impurity concentration than the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.